A master's thesis at the College of Engineering, University of Basra, is being discussed FPGA-Based Design and implementation of Multilevel Image Encryption System

The master's thesis of researcher Zainab Karim Ibrahim was discussed at the College of Engineering, University of Basra, entitled FPGA-Based Design and implementation of Multilevel Image Encryption System Due to the rapid increase of data sharing over communication networks and because of the networks' insecurity and vulnerability to hacking, more algorithms have been found and developed to protect data. Visual data, like images, is widely used in many important and sensitive fields, so the demand increases to find a fast and secure cryptographic system to protect images. Utilisingchaos theory in cryptography makes sense in terms ofsecurity robustness due to its properties, such as sensitivity to initial conditions and control parameters. These properties are exactly the requirements needed by the cryptographic system. Implementing a chaos-based cryptographic system physically on a programmable board will add speed property in addition to security robustness.
This thesis presents a systematic, incremental demonstration of implementing a hardware cryptographic system, using an Artix A7 Field Programmable Gate Array (FPGA) board implementation. Progressing towards a more sophisticated design, the final proposed architecture was accurately evaluated and shows superior performance in terms of both processing speed and security robustness. All the proposed hardware cryptographic systems were designed using the Xilinx System Generator (XSG) tool to facilitate the design, simulation, and implementation of any system and save time and effort. 
The first proposed hardware cryptographic system was a single-level, permutation-only, and chaos-based cryptographic system. Three systems were designed, implemented, and evaluated based on Henon, Duffing, and Arnold’s Cat chaotic maps. The Henon-based cryptographic system shows high speedup when compared with its corresponding software program, ranging from 132 to 3 for grayscale images and from 185 to 5.8 for RGB images, but consumes high resources from the Artix A7 FPGA board. The second Duffing-based cryptographic system shows lower speedup, ranging from 94 to 4 for grayscale images and from 181 to 11 for RGB images, with small resource utilisation. The third Arnold’s Cat-based cryptographic system shows a balance between resource utilisation and speedup.
The second proposed hardware cryptographic system was a permutation-substitution, dual-level cryptographic system. In the first proposed design, the permutation was Duffing-based, with Henon-based substitution. This design showed a slight enhancement in the security robustness as compared with a single-level cryptographic system. To add more complexity to the dual-level cryptographic system, three chaotic maps are cooperated for the substitution level. This modification added strength to the cryptographic system, depending on the CCA values that decayed from an absolute 0.0517 to 0.0039 for grayscale 128×128, while the NPCR improved from 99.6995% to 99.7855% for the same image size and type. In hardware performance, the enhanced dual-level attains speed up factors of 109.5 to 5 for 128×128 to 1024×1024 grayscale images and 206.9 to 7.5 for RGB images
The third proposed hardware cryptographic system was a multi-level cryptographic system. The first proposed design consists of a permutation-level based on Arnold’s Cat map, a substitution-level based on Henon, Tent, and Logistic chaotic maps, followed by another substitution level based on Linear Feedback Shift Register (LFSR). This design achieved high security robustness, which is represented by a lower correlation between adjacent pixels. For 128×128, it ranges from 0.0001 to 0.0003 for the encrypted grayscale images and from 0.0001 to 0.00041 for the encrypted RGB images.
The final proposed design was a multi-round cryptographic system. By rounding the dual-level system for some rounds, the results were high security with adequate resource utilisation, with high speed up ranges from 118.7 to 6 for 128×128 to 1024×1024 grayscale images, and from 277 to 12 for 128×128 to 1024×1024 RGB images, respectively.